Path: ...!eternal-september.org!feeder3.eternal-september.org!news.quux.org!news.nk.ca!rocksolid2!i2pn2.org!.POSTED!not-for-mail From: mitchalsup@aol.com (MitchAlsup1) Newsgroups: comp.arch Subject: Re: Is Parallel Programming Hard, And, If So, What Can You Do About =?UTF-8?B?SXQ/?= Date: Mon, 12 May 2025 00:30:37 +0000 Organization: Rocksolid Light Message-ID: <0ec5d195f4732e6c92da77b7e2fa986d@www.novabbs.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Info: i2pn2.org; logging-data="4149740"; mail-complaints-to="usenet@i2pn2.org"; posting-account="o5SwNDfMfYu6Mv4wwLiW6e/jbA93UAdzFodw5PEa6eU"; User-Agent: Rocksolid Light X-Rslight-Posting-User: cb29269328a20fe5719ed6a1c397e21f651bda71 X-Spam-Checker-Version: SpamAssassin 4.0.0 X-Rslight-Site: $2y$10$oM4tFu8ARo8c0DJsDfgbnOCMjJx6MfjPXGLIzpynUq4F0UvO7Bxhy Bytes: 1620 Lines: 13 On Sun, 11 May 2025 23:46:17 +0000, Lawrence D'Oliveiro wrote: > On Sun, 11 May 2025 07:47:53 -0700, Al Kossow wrote: > >> With the narrow memory interfaces, are cores starved for memory >> bandwidth? > > Low memory bandwidth has been a chronic issue since the “wait states” of > the 1980s. > > That’s why we have memory caches. Which architects tend to only understand what happens when these caches are attached to CPUs and not "Joe Random Bus Master",