Path: news.eternal-september.org!eternal-september.org!feeder3.eternal-september.org!i2pn.org!i2pn2.org!.POSTED!not-for-mail From: quadibloc Newsgroups: comp.arch Subject: Why I've Dropped In Date: Mon, 19 May 2025 19:15:36 +0000 Organization: novaBBS Message-ID: <0c857b8347f07f3a0ca61c403d0a8711@www.novabbs.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Info: i2pn2.org; logging-data="1065765"; mail-complaints-to="usenet@i2pn2.org"; posting-account="GSAUMsvIs05PgSAevbIzdWiOy1BcuThtiv166p5NnMk"; User-Agent: Rocksolid Light X-Rslight-Posting-User: 7260c650ae4d5ba82d3b6b1eab0ac1b8653ff052 X-Rslight-Site: $2y$10$ZOmn88yAAa13N3K5njhNyet0EdmVzIlzUZqsA8S3QCFaiZDzcUaR. X-Spam-Checker-Version: SpamAssassin 4.0.0 I haven't posted in this newsgroup for a while. In case anyone has wondered why I've visited once again, it's for the obvious reason. I've turned my attention again to Concertina II. I thought that I had a great idea to reduce the overhead for certain block types. Then I saw it had a flaw, But I could fix that flaw, but it resulted in an inelegant asymmetry. Then I saw how to fix that! And then I realized the fix still was missing something important. So there will be some delay before I take another step in going around in circles with Concertina II. My brilliant idea? Reduce the displacements from 16 bits to 15, so that memory-reference instructions could fit in 1/4 of the opcode space. Then I could have blocks with variable-length instructions, as long as I didn't allow instructions to cross block boundaries, with only 16 bits of overhead. But I knew I would never stay satisfied with only 15-bit displacements. On further thought, I thought that I could still have 16-bit displacements, and have a complete instruction set. But I ended up realizing that I wouldn't have a complete instruction set for the blocks with variable-length instructions. John Savard