Deutsch English Français Italiano |
<v09p38$1uqd3$2@dont-email.me> View for Bookmarking (what is this?) Look up another Usenet article |
Path: ...!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Don Y <blockedofcourse@foo.invalid> Newsgroups: sci.electronics.design Subject: Re: Zilog stopping Z80 production Date: Tue, 23 Apr 2024 19:00:00 -0700 Organization: A noiseless patient Spider Lines: 15 Message-ID: <v09p38$1uqd3$2@dont-email.me> References: <v07k2p$cki9$1@solani.org> <v09ih8$bfo$1@nnrp.usenet.blueworldhosting.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 24 Apr 2024 04:00:10 +0200 (CEST) Injection-Info: dont-email.me; posting-host="d85e5b9915e519df6b3caffff780075d"; logging-data="2058659"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX198NxsIxVqODp8SzDa5y5T5" User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Cancel-Lock: sha1:C7Tm2cvQs5vpV9HZVb0IHtnvThQ= In-Reply-To: <v09ih8$bfo$1@nnrp.usenet.blueworldhosting.com> Content-Language: en-US Bytes: 1723 On 4/23/2024 5:08 PM, Edward Rawde wrote: > It must be trivial to get a VHDL/Verilog model and make your own by now. The problem with all the early/simple/trivial processors is getting the rest of the system to run as fast as the core can. E.g., running a core at ~200MHz and expecting the same bus timing means < 5ns memory. (for a Z80, that would be ~10ns as the bus timing is inherently slower) The better option is to embed the core *in* a design to give you the advantages of a programmable sequencer (instead of "junk logic") > The 6809 was my preference but took a few more years.