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From: Don Y <blockedofcourse@foo.invalid>
Newsgroups: sci.electronics.design
Subject: Re: Zilog stopping Z80 production
Date: Wed, 24 Apr 2024 17:57:40 -0700
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On 4/24/2024 3:39 PM, Lasse Langwadt wrote:
> On 4/24/24 22:48, boB wrote:
>> On Wed, 24 Apr 2024 21:22:07 +0200, Lasse Langwadt <llc@fonz.dk>
>> wrote:
>>
>>> On 4/24/24 04:00, Don Y wrote:
>>>> On 4/23/2024 5:08 PM, Edward Rawde wrote:
>>>>> It must be trivial to get a VHDL/Verilog model and make your own by now.
>>>>
>>>> The problem with all the early/simple/trivial processors is getting
>>>> the rest of the system to run as fast as the core can.  E.g., running
>>>> a core at ~200MHz and expecting the same bus timing means < 5ns memory.
>>>>
>>>> (for a Z80, that would be ~10ns as the bus timing is inherently slower)
>>>>
>>>
>>> how much memory can it address?
>>>
>>
>> 64K
>> 16 bits worth.
> 
> so in something like and FPGA in is with range of internal ram and memory speed 
> is not really an issue

A processor that can't talk to the outside world (using the interface defined
by the original device) is essentially a gum drop, sitting on a shelf...