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From: Waldek Hebisch <antispam@fricas.org>
Newsgroups: comp.lang.c
Subject: Re: Top 10 most common hard skills listed on resumes...
Date: Sun, 8 Sep 2024 21:34:27 -0000 (UTC)
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David Brown <david.brown@hesbynett.no> wrote:
> 
> And while microcontrollers sometimes have a limited form of branch 
> prediction (such as prefetching the target from cache), the more 
> numerous and smaller devices don't even have instruction caches. 
> Certainly none of them have register renaming or speculative execution.

IIUC STM4 series has cache, and some of them are not so big.  There
are now several chinese variants of STM32F103 and some of them have
caches (some very small like 32 words, IIRC one has 8 words and it
is hard to decide if this very small cache or big prefetch buffer).
A notable example is MH32F103.  Base model officially has 64kB RAM and
256KB flash.  AFAIK this flash is rather slow SPI flash.  It also
has 16kB cache which probably is 4-way set associative with few
extra lines (probably 4) to increase apparent associativity.
I write probably because this is result of reasoning based on
several time measurements.  If you hit cache it runs nicely at
216 MHz.  Cache miss costs around 100 clocks (varies depending on
exact setting of timing parameters and form of access).

Similar technology seem to be popular among chines chip makers,
especially for "bigger" chips.  But IIUC GD use is for chips
of size of STM32F103C8T6.

-- 
                              Waldek Hebisch