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From: "Edward Rawde" <invalid@invalid.invalid>
Newsgroups: sci.electronics.design
Subject: Re: High purity 1kHz oscillator
Date: Tue, 22 Oct 2024 10:12:23 -0400
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"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vf7slm$1e357$1@dont-email.me...
> On 22/10/2024 4:10 pm, Edward Rawde wrote:
>> But I suspect that component tolerances and mismatched FETs will ruin it.
>>
>> Otherwise it should be easy to get 60dB down on unwanted harmonics with a better filter.
>>
>> FWIW I likely won't be here for the next week.
>
> <snip>
>
> My message was that the current sucked out of U2 through D1 and D2 was a narrow spike, peaking at 0.3mA and repeating at 1kHz, 
> which distorted the voltage at the output of U2.
>
> Your revised circuit persists with this mistake, and the filter you've added around U1 doesn't do enough to compensate.

That's what I thought you'd say, because there are now two spikes, but it does seem to reduce distortion.
So I'd leave it in any experimental prototype and take the decision to remove it if real testing shows it's not sufficiently 
beneficial.
The filter can be redesigned when a real circuit is tested. I didn't have time to do a more elaborate active filter.

>
> Using two FETs as your adjustable resistance does seem to get rid of the even-order harmonics, but it doesn't make enough 
> difference to be worth the effort.
>
> I do worry about component tolerances, and they won't make much difference to the circuit. Neither will mismatched FETs. The 
> capacitative feedthough via the gate into the FET conduction channels is probably more of a worry, and that's built into the 
> LTSpice FET model.
>
> Bad layout can wreck pretty much any well-designed circuit, let alone badly designed ones. My professional career included a bit 
> of cleaning up such layouts.

I've had management think that a "proper" layout will turn a badly designed prototype circuit into something which does not need to 
be redesigned.

>
> -- 
> Bill Sloman, Sydney